A Designer’s Guide to Built-In Self-Test by Charles E. Stroud

By Charles E. Stroud

A contemporary technological enhance is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept was once first proposed round 1980 and has grown to turn into some of the most very important trying out concepts on the present time, in addition to for the long run. This booklet is written from a designer's point of view and describes the key BIST techniques which were proposed and applied due to the fact that 1980, besides their benefits and boundaries. The BIST ways comprise the integrated good judgment Block Observer, pseudo-exhaustive BIST suggestions, round BIST, scan-based BIST, BIST for normal constructions, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection suggestions for online trying out. specific realization is paid to system-level use of BIST to be able to maximize some great benefits of BIST via lowered checking out time and price in addition to excessive diagnostic solution. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 creation VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of assorted forms for normal buildings and common sequential common sense, together with the 1st BIST for Random entry thoughts (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal platforms at Bell Labs. He has spent the previous 10 years in academia the place his examine and improvement keeps to target BIST, together with the 1st BIST for FPGAs and CPLDs in addition to endured paintings within the region of BIST for normal sequential good judgment and mixed-signal platforms. He holds 10 US patents (with five extra pending) for numerous sorts of BIST methods. hence, the writer brings a special mix of data and adventure to this functional consultant for designers, try engineers, product engineers, approach diagnosticians, and managers.

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Otherwise, fault sampling provides an excellent method of reducing fault simulation time for very large circuits with minimal loss of accuracy in fault coverage determination. 1). However, there are other factors that influence the fault coverage calculation. These include undetectable and potentially detected faults, both of which can lower the overall fault coverage that be obtained for most circuits unless one specifically considers these types of faults and how to deal with them in the fault coverage calculation.

As a result, the testability of the entire circuit is a function of the controllability and observability of all fault sites within the complete circuit. 2 Path Sensitization The controllability and observability of a fault site can most easily be seen through the path sensitization algorithm for determining test vectors that will detect gate-level stuck-at faults in a combinational logic circuit with no feedback paths. This algorithm provides the basic idea behind many ATPG programs [4].

As a result, the single fault model is widely used for test development and evaluation. Unless specifically stated otherwise, the single fault model will be assumed in the subsequent sections and chapters. 6 Equivalent Faults and Fault Collapsing Under the single fault model, the number of gate-level stuck-at faults associated with each gate is twice the total number of inputs and outputs of the gate since each input or output can be either stuck-at-0 or stuck-at-1. 3 it is evident that some of these faults behave identically and cannot be distinguished from each other as a result of their faulty behavior.

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