Advanced Interconnects for ULSI Technology by Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech

By Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech

Discovering new fabrics for copper/low-k interconnects is necessary to the continued improvement of desktop chips. whereas copper/low-k interconnects have served good, taking into consideration the construction of extremely huge Scale Integration (ULSI) units which mix over 1000000000 transistors onto a unmarried chip, the elevated resistance and RC-delay on the smaller scale has turn into a major factor affecting chip functionality.

Advanced Interconnects for ULSI Technology is devoted to the fabrics and techniques that can be appropriate replacements. It covers a wide variety of issues, from actual rules to layout, fabrication, characterization, and alertness of recent fabrics for nano-interconnects, and discusses:

  • Interconnect features, characterisations, electric homes and wiring specifications
  • Low-k fabrics: basics, advances and mechanical  houses
  • Conductive layers and boundaries
  • Integration and reliability together with mechanical reliability, electromigration and electric breakdown
  • New methods together with 3D, optical, instant interchip, and carbon-based interconnects

Intended for postgraduate scholars and researchers, in academia and undefined, this e-book offers a severe assessment of the permitting expertise on the center of the longer term improvement of desktop chips.

Content:
Chapter 1 Low?k fabrics: fresh Advances (pages 1–33): Geraud Dubois and Willi Volksen
Chapter 2 Ultra?Low?k by means of CVD: Deposition and Curing (pages 35–77): Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov
Chapter three Plasma Processing of Low?k Dielectrics (pages 79–128): Hualiang Shi, Denis Shamiryan, Jean?Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov
Chapter four rainy fresh purposes in Porous Low?k Patterning procedures (pages 129–171): Quoc Toan Le, man Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov
Chapter five Copper Electroplating for On?Chip Metallization (pages 173–191): Valery M. Dubin
Chapter 6 Diffusion limitations (pages 193–234): Michael Hecker and Rene Hubner
Chapter 7 method Integration of Interconnects (pages 235–265): Sridhar Balakrishnan, Ruth mind and Larry Zhao
Chapter eight Chemical Mechanical Planarization for Cu–Low?k Integration (pages 267–289): Gautam Banerjee
Chapter nine Scaling and Microstructure results on Electromigration Reliability for Cu Interconnects (pages 291–337): Chao?Kun Hu, Rene Hubner, Lijuan Zhang, Meike Hauschildt and Paul S. Ho
Chapter 10 Mechanical Reliability of Low?k Dielectrics (pages 339–367): Kris Vanstreels, Han Li and Joost J. Vlassak
Chapter eleven electric Breakdown in complex Interconnect Dielectrics (pages 369–434): Ennis T. Ogawa and Oliver Aubel
Chapter 12 3D Interconnect expertise (pages 435–490): John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
Chapter thirteen Carbon Nanotubes for Interconnects (pages 491–502): Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano
Chapter 14 Optical Interconnects (pages 503–542): Wim Bogaerts
Chapter 15 instant Interchip Interconnects (pages 543–563): Takamaro Kikkawa

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In fact, the majority of the sidewall damage can be attributed to the strip (ash) of the remaining photoresist. Whereas the etch plasma damage to the via-sidewall is primarily confined to the surface, a PR plasma strip may induce damage that extends far into the bulk of the ILD and is a function of the overall porosity, pore size and pore interconnectivity. Following patterning of the via-structure, the line level has to be lithographically defined. In order to allow for uniform coverage of the photoresist on top of the viastructures, the topography has to be planarized.

5Å) low-k material, incorporation of nanosized voids using γ-cyclodextrin as a porogen was explored [140]. 29 nm was created. The dielectric constant decreases in relation to the amount of porogen used. 3 GPa by nanoindentation). Unfortunately, all of the cyclodextrin containing films required heating to 450 oC for 9 h to ensure full decomposition of the porogens (cyclodextrin and TPAOH), making this process unsuitable for integration. indd 17 12/20/2011 12:45:56 PM 18 Advanced Interconnects for ULSI Technology Because all the films above are composed of a mixture of amorphous silica and silicalite nanocrystals, not only the overall ratio of one silica component versus the other (in other words the total level of film crystallinity) [141] but also the nature of the zeolite (MFI or MEL, zeolites with a two-dimensional 10-ring pore structure) [142] influence the dielectric properties of the material.

However, as line and via dimensions shrink in accordance with future technology nodes, thinner barrier layers are needed to maintain or improve electrical performance. 0. Next, copper is deposited into the patterned dualdamascene structure and the Cu overburden including the bilayer hardmask is polished back to the ILD using chemical mechanical polishing (CMP). 3 (i) ). Proper selection of the CMP slurries in addition to low down-force CMP processes can significantly mitigate these problems. Finally, the last step in the dual-damascene process involves the deposition of a capping layer to protect the oxidatively sensitive Cu metallurgy, so that the entire process sequence can be repeated over and over again.

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